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fix: fix esp_afe_sr_iface_t compile error (#1423)

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* fix: fix esp_afe_sr_iface_t compile error

* fix: fix `MIPI_DSI_PHY_CLK_SRC_DEFAULT` compile error in IDF 5.5.2
This commit is contained in:
laride
2025-11-13 20:05:42 +08:00
committed by GitHub
parent 30970abd1f
commit 92de37e182
7 changed files with 2 additions and 8 deletions
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1
main/boards/m5stack-tab5/esp_lcd_st7123.h
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@@ -75,7 +75,6 @@
{ \
.bus_id = 0, \
.num_data_lanes = 2, \
.phy_clk_src = MIPI_DSI_PHY_CLK_SRC_DEFAULT, \
.lane_bit_rate_mbps = 1000, \
}

2
main/boards/m5stack-tab5/m5stack_tab5.cc
View File

@@ -198,7 +198,6 @@ private:
esp_lcd_dsi_bus_config_t bus_config = {
.bus_id = 0,
.num_data_lanes = 2,
.phy_clk_src = MIPI_DSI_PHY_CLK_SRC_DEFAULT,
.lane_bit_rate_mbps = 900, // 900MHz
};
ESP_ERROR_CHECK(esp_lcd_new_dsi_bus(&bus_config, &mipi_dsi_bus));
@@ -283,7 +282,6 @@ private:
/* create MIPI DSI bus first, it will initialize the DSI PHY as well */
bus_config.bus_id = 0;
bus_config.num_data_lanes = 2; // ST7123 uses 2 data lanes
bus_config.phy_clk_src = MIPI_DSI_PHY_CLK_SRC_DEFAULT;
bus_config.lane_bit_rate_mbps = 965; // ST7123 lane bitrate
ret = esp_lcd_new_dsi_bus(&bus_config, &mipi_dsi_bus);
if (ret != ESP_OK) {